IEEE Standard 1500 Compliance Verification for Embedded Cores

On IEEE P1500's Standard for Embedded Core Test

The increased usage of embedded pre-designed reusable cores necessitates a core-based test strategy, in which cores are tested as separate entities. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-underdevelopment that aims at improving ease of reuse and facilitating interoperability with respect to the test of core-based system chips, especially if they contain cores from diffe...

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficien...

Automating IEEE 1500 Core Test—An EDA Perspective

THE CURRENT TREND of SoC design has made conventional test methodologies increasingly difficult. Performing brute-force test pattern generation (ATPG) on the entire SoC is often infeasible, because the design can exceed the test pattern generator’s capabilities. At other times, some black-box third-party cores within the SoC might have their own test patterns generated at the core boundary. IEE...

Ensuring Schedulability for Embedded Multi-cores

Verification Patterns for Rapid Embedded System Verification

Test result verification is always a costly task for embedded system testing. This paper presents a systematic process to develop verification patterns and use these patterns to verify test results for state-based real-time/embedded systems. The verification patterns are organized into an object-oriented verification framework so that it can be adaptive to changes rapidly The verification patte...